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FOC电机控制示例源码 ​

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1839 个文件918 个目录29.6 MB 解压后大小
H667C441S258SCT240LD114MAT24UVOPTX21UVPROJX21ICF18YML12IOC6TXT6
查看完整目录 · 1839 个文件
   1.4 KB  FOC_base/Core/Inc/adc.h
   1.3 KB  FOC_base/Core/Inc/comp.h
   1.4 KB  FOC_base/Core/Inc/dac.h
   1.4 KB  FOC_base/Core/Inc/dma.h
   1.3 KB  FOC_base/Core/Inc/gpio.h
   2.4 KB  FOC_base/Core/Inc/main.h
   1.5 KB  FOC_base/Core/Inc/opamp.h
  13.0 KB  FOC_base/Core/Inc/stm32g4xx_hal_conf.h
   2.2 KB  FOC_base/Core/Inc/stm32g4xx_it.h
   1.4 KB  FOC_base/Core/Inc/tim.h
   1.3 KB  FOC_base/Core/Inc/usart.h
  10.6 KB  FOC_base/Core/Src/adc.c
   2.8 KB  FOC_base/Core/Src/comp.c
   4.7 KB  FOC_base/Core/Src/dac.c
   1.6 KB  FOC_base/Core/Src/dma.c
   2.3 KB  FOC_base/Core/Src/gpio.c
  10.4 KB  FOC_base/Core/Src/main.c
   6.6 KB  FOC_base/Core/Src/opamp.c
   2.3 KB  FOC_base/Core/Src/stm32g4xx_hal_msp.c
   9.4 KB  FOC_base/Core/Src/stm32g4xx_it.c
  10.3 KB  FOC_base/Core/Src/system_stm32g4xx.c
   6.9 KB  FOC_base/Core/Src/tim.c
   4.9 KB  FOC_base/Core/Src/usart.c
  19.2 KB  FOC_base/MDK-ARM/startup_stm32g431xx.s
  21.4 KB  FOC_base/MDK-ARM/STM32G4_GPIO.uvoptx
  63.7 KB  FOC_base/MDK-ARM/STM32G4_GPIO.uvprojx
    494 B  FOC_base/MDK-ARM/STM32G4_GPIO/STM32G4_GPIO.sct
  14.0 KB  FOC_base/STM32G4_GPIO.ioc
   3.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Config/mem_ARMCA5.h
   1.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Config/system_ARMCA5.h
   8.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Include/ARMCA5.h
   2.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/AC5/ARMCA5.sct
   5.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/AC6/ARMCA5.sct
   6.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c
   3.9 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/GCC/ARMCA5.ld
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/GCC/ARMCA5.sct
   6.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c
   3.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/IAR/ARMCA5.icf
   4.1 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s
  13.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/mmu_ARMCA5.c
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA5/Source/system_ARMCA5.c
   3.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Config/mem_ARMCA7.h
   1.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Config/system_ARMCA7.h
   8.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Include/ARMCA7.h
   2.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Source/AC5/ARMCA7.sct
   5.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Source/AC6/ARMCA7.sct
   6.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c
   3.9 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Source/GCC/ARMCA7.ld
   6.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c
   3.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Source/IAR/ARMCA7.icf
   4.1 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s
  13.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Source/mmu_ARMCA7.c
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA7/Source/system_ARMCA7.c
   3.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Config/mem_ARMCA9.h
   1.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Config/system_ARMCA9.h
   8.9 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Include/ARMCA9.h
   2.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Source/AC5/ARMCA9.sct
   5.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Source/AC6/ARMCA9.sct
   6.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c
   3.9 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Source/GCC/ARMCA9.ld
   6.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c
   3.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Source/IAR/ARMCA9.icf
   4.1 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s
  13.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Source/mmu_ARMCA9.c
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCA9/Source/system_ARMCA9.c
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0/Include/ARMCM0.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0/Include/system_ARMCM0.h
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0/Source/ARM/ARMCM0_ac5.sct
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0/Source/ARM/ARMCM0_ac6.sct
   6.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0/Source/GCC/gcc_arm.ld
   7.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S
   5.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s
   6.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0/Source/startup_ARMCM0.c
   2.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0/Source/system_ARMCM0.c
   4.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Include/ARMCM0plus.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct
   6.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld
   7.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S
   5.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s
   6.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Source/startup_ARMCM0plus.c
   2.1 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM1/Include/ARMCM1.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM1/Include/system_ARMCM1.h
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM1/Source/ARM/ARMCM1_ac5.sct
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM1/Source/ARM/ARMCM1_ac6.sct
   6.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM1/Source/GCC/gcc_arm.ld
   7.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S
   5.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s
   6.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM1/Source/startup_ARMCM1.c
   2.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM1/Source/system_ARMCM1.c
   4.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Include/ARMCM23_TZ.h
   4.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Include/ARMCM23.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Include/system_ARMCM23.h
  28.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct
   6.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.S
   7.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Source/GCC/gcc_arm.ld
   7.9 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S
   6.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Source/startup_ARMCM23.c
   2.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM23/Source/system_ARMCM23.c
   4.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM3/Include/ARMCM3.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM3/Include/system_ARMCM3.h
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct
   6.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM3/Source/GCC/gcc_arm.ld
   7.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S
   5.9 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s
   6.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM3/Source/startup_ARMCM3.c
   2.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM3/Source/system_ARMCM3.c
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Include/ARMCM33_TZ.h
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Include/ARMCM33.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Include/system_ARMCM33.h
  48.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.S
   7.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Source/GCC/gcc_arm.ld
   8.1 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S
   6.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s
   7.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Source/startup_ARMCM33.c
   3.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM33/Source/system_ARMCM33.c
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Include/ARMCM35P.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Include/system_ARMCM35P.h
  48.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.S
   7.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld
   8.1 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S
   6.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s
   7.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Source/startup_ARMCM35P.c
   3.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM35P/Source/system_ARMCM35P.c
   4.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Include/ARMCM4_FP.h
   4.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Include/ARMCM4.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Include/system_ARMCM4.h
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct
   6.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Source/GCC/gcc_arm.ld
   7.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S
   5.9 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Source/startup_ARMCM4.c
   2.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM4/Source/system_ARMCM4.c
   5.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM55/Include/ARMCM55.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM55/Include/system_ARMCM55.h
  48.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM55/Include/Template/partition_ARMCM55.h
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6_s.sct
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct
   7.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM55/Source/GCC/gcc_arm.ld
   7.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM55/Source/startup_ARMCM55.c
   3.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM55/Source/system_ARMCM55.c
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Include/ARMCM7_DP.h
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Include/ARMCM7_SP.h
   5.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Include/ARMCM7.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Include/system_ARMCM7.h
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct
   6.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Source/GCC/gcc_arm.ld
   7.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S
   5.9 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Source/startup_ARMCM7.c
   2.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM7/Source/system_ARMCM7.c
   5.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM85/Include/ARMCM85.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM85/Include/system_ARMCM85.h
  49.1 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM85/Include/Template/partition_ARMCM85.h
   4.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6_s.sct
   4.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6.sct
   7.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM85/Source/GCC/gcc_arm.ld
   7.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM85/Source/startup_ARMCM85.c
   3.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMCM85/Source/system_ARMCM85.c
   4.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC000/Include/ARMSC000.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC000/Include/system_ARMSC000.h
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct
   6.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC000/Source/GCC/gcc_arm.ld
   7.2 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S
   5.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s
   6.3 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC000/Source/startup_ARMSC000.c
   2.0 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC000/Source/system_ARMSC000.c
   4.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC300/Include/ARMSC300.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC300/Include/system_ARMSC300.h
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct
   2.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct
   6.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s
   6.8 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC300/Source/GCC/gcc_arm.ld
   7.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S
   5.9 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s
   6.7 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC300/Source/startup_ARMSC300.c
   2.5 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMSC300/Source/system_ARMSC300.c
   5.4 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h
   1.6 KB  FOC_base/VSCODE/.cmsis/device/ARM/ARMv81MML/Include/system_ARMv81MML.h
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    306 B  README.txt

可读文件预览

README.txt306 B
FOC电机控制示例源码

本压缩包由开源协会知识库从学习目录中自动精选生成。
已排除安装包、视频、编译缓存、目标文件、可执行文件、私钥和大型第三方依赖。
部分工程需要通过对应 IDE、SDK 或配置文件重新生成依赖后再编译。
FOC_Clark_Park/.pack/Keil/STM32G4xx_DFP.1.1.0/MDK/Boards/ST/STM32G474E-EVAL/Blinky/Abstract.txt749 B
The 'Blinky' project is a simple CMSIS RTOS2 based example for
ST 'STM32G474QE' microcontroller using ST 'STM32G474E-EVAL' Board.
Compliant to Cortex Microcontroller Software Interface Standard (CMSIS).

Example functionality:
 - Clock Settings:
   - HSI     =           16 MHz
   - SYSCLK  =          170 MHz

 - 4 LEDs blink with fixed speed.
 - blinking is paused while holding down USER button.


The Blinky program is available in different targets:
 - Debug:
   - Compiler optimization Level 1
   - Enabled Event Recorder
   - Keil RTX5 variant 'Source'
 - Release:
   - Compiler optimization Level 3
   - Keil RTX5 variant 'Library'

Note:
 CubeMX configuration is taken from 'CubeMX Board Selector: STM32G474E-EVAL'
FOC_Clark/.pack/Keil/STM32G4xx_DFP.1.1.0/MDK/Boards/ST/STM32G474E-EVAL/Blinky/Abstract.txt749 B
The 'Blinky' project is a simple CMSIS RTOS2 based example for
ST 'STM32G474QE' microcontroller using ST 'STM32G474E-EVAL' Board.
Compliant to Cortex Microcontroller Software Interface Standard (CMSIS).

Example functionality:
 - Clock Settings:
   - HSI     =           16 MHz
   - SYSCLK  =          170 MHz

 - 4 LEDs blink with fixed speed.
 - blinking is paused while holding down USER button.


The Blinky program is available in different targets:
 - Debug:
   - Compiler optimization Level 1
   - Enabled Event Recorder
   - Keil RTX5 variant 'Source'
 - Release:
   - Compiler optimization Level 3
   - Keil RTX5 variant 'Library'

Note:
 CubeMX configuration is taken from 'CubeMX Board Selector: STM32G474E-EVAL'
FOC_base/Core/Src/adc.c10.6 KB
/* USER CODE BEGIN Header */
/**
  ******************************************************************************
  * @file    adc.c
  * @brief   This file provides code for the configuration
  *          of the ADC instances.
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2025 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "adc.h"

/* USER CODE BEGIN 0 */

/* USER CODE END 0 */

ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc2;

/* ADC1 init function */
void MX_ADC1_Init(void)
{

  /* USER CODE BEGIN ADC1_Init 0 */

  /* USER CODE END ADC1_Init 0 */

  ADC_MultiModeTypeDef multimode = {0};
  ADC_ChannelConfTypeDef sConfig = {0};
  ADC_InjectionConfTypeDef sConfigInjected = {0};

  /* USER CODE BEGIN ADC1_Init 1 */

  /* USER CODE END ADC1_Init 1 */

  /** Common config
  */
  hadc1.Instance = ADC1;
  hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
  hadc1.Init.GainCompensation = 0;
  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
  hadc1.Init.LowPowerAutoWait = DISABLE;
  hadc1.Init.ContinuousConvMode = DISABLE;
  hadc1.Init.NbrOfConversion = 1;
  hadc1.Init.DiscontinuousConvMode = DISABLE;
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
  hadc1.Init.DMAContinuousRequests = DISABLE;
  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
  hadc1.Init.OversamplingMode = DISABLE;
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure the ADC multi-mode
  */
  multimode.Mode = ADC_MODE_INDEPENDENT;
  if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_11;
  sConfig.Rank = ADC_REGULAR_RANK_1;
  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
  sConfig.Offset = 0;
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Injected Channel
  */
  sConfigInjected.InjectedChannel = ADC_CHANNEL_3;
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_1;
  sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_2CYCLES_5;
  sConfigInjected.InjectedSingleDiff = ADC_SINGLE_ENDED;
  sConfigInjected.InjectedOffsetNumber = ADC_OFFSET_NONE;
  sConfigInjected.InjectedOffset = 0;
  sConfigInjected.InjectedNbrOfConversion = 2;
  sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
  sConfigInjected.AutoInjectedConv = DISABLE;
  sConfigInjected.QueueInjectedContext = DISABLE;
  sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJEC_T1_CC4;
  sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONV_EDGE_RISING;
  sConfigInjected.InjecOversamplingMode = DISABLE;
  if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Injected Channel
  */
  sConfigInjected.InjectedChannel = ADC_CHANNEL_12;
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_2;
  if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN ADC1_Init 2 */
  
  /* USER CODE END ADC1_Init 2 */

}
/* ADC2 init function */
void MX_ADC2_Init(void)
{

  /* USER CODE BEGIN ADC2_Init 0 */

  /* USER CODE END ADC2_Init 0 */

  ADC_ChannelConfTypeDef sConfig = {0};
  ADC_InjectionConfTypeDef sConfigInjected = {0};

  /* USER CODE BEGIN ADC2_Init 1 */

  /* USER CODE END ADC2_Init 1 */

  /** Common config
  */
  hadc2.Instance = ADC2;
  hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
  hadc2.Init.Resolution = ADC_RESOLUTION_12B;
  hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
  hadc2.Init.GainCompensation = 0;
  hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
  hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
  hadc2.Init.LowPowerAutoWait = DISABLE;
  hadc2.Init.ContinuousConvMode = DISABLE;
  hadc2.Init.NbrOfConversion = 1;
  hadc2.Init.DiscontinuousConvMode = DISABLE;
  hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
  hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
  hadc2.Init.DMAContinuousRequests = DISABLE;
  hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
  hadc2.Init.OversamplingMode = DISABLE;
  if (HAL_ADC_Init(&hadc2) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_3;
  sConfig.Rank = ADC_REGULAR_RANK_1;
  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
  sConfig.Offset = 0;
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Injected Channel
  */
  sConfigInjected.InjectedChannel = ADC_CHANNEL_3;
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_1;
  sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_2CYCLES_5;
  sConfigInjected.InjectedSingleDiff = ADC_SINGLE_ENDED;
  sConfigInjected.InjectedOffsetNumber = ADC_OFFSET_NONE;
  sConfigInjected.InjectedOffset = 0;
  sConfigInjected.InjectedNbrOfConversion = 1;
  sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
  sConfigInjected.AutoInjectedConv = DISABLE;
  sConfigInjected.QueueInjectedContext = DISABLE;
  sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJEC_T1_CC4;
  sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONV_EDGE_RISING;
  sConfigInjected.InjecOversamplingMode = DISABLE;
  if (HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN ADC2_Init 2 */

  /* USER CODE END ADC2_Init 2 */

}

static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0;

void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{

  GPIO_InitTypeDef GPIO_InitStruct = {0};
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
  if(adcHandle->Instance==ADC1)
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */

  /** Initializes the peripherals clocks
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
    PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
    {
      Error_Handler();
    }

    /* ADC1 clock enable */
    HAL_RCC_ADC12_CLK_ENABLED++;
    if(HAL_RCC_ADC12_CLK_ENABLED==1){
      __HAL_RCC_ADC12_CLK_ENABLE();
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();
    __HAL_RCC_GPIOB_CLK_ENABLE();
    /**ADC1 GPIO Configuration
    PA2     ------> ADC1_IN3
    PB1     ------> ADC1_IN12
    PB12     ------> ADC1_IN11
    */
    GPIO_InitStruct.Pin = GPIO_PIN_2;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_12;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

    /* ADC1 interrupt Init */
    HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
  /* USER CODE BEGIN ADC1_MspInit 1 */

  /* USER CODE END ADC1_MspInit 1 */
  }
  else if(adcHandle->Instance==ADC2)
  {
  /* USER CODE BEGIN ADC2_MspInit 0 */

  /* USER CODE END ADC2_MspInit 0 */

  /** Initializes the peripherals clocks
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
    PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
    {
      Error_Handler();
    }

    /* ADC2 clock enable */
    HAL_RCC_ADC12_CLK_ENABLED++;
    if(HAL_RCC_ADC12_CLK_ENABLED==1){
      __HAL_RCC_ADC12_CLK_ENABLE();
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();
    /**ADC2 GPIO Configuration
    PA0     ------> ADC2_IN1
    PA6     ------> ADC2_IN3
    */
    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_6;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

    /* ADC2 interrupt Init */
    HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
  /* USER CODE BEGIN ADC2_MspInit 1 */

  /* USER CODE END ADC2_MspInit 1 */
  }
}

void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
{

  if(adcHandle->Instance==ADC1)
  {
  /* USER CODE BEGIN ADC1_MspDeInit 0 */

  /* USER CODE END ADC1_MspDeInit 0 */
    /* Peripheral clock disable */
    HAL_RCC_ADC12_CLK_ENABLED--;
    if(HAL_RCC_ADC12_CLK_ENABLED==0){
      __HAL_RCC_ADC12_CLK_DISABLE();
    }

    /**ADC1 GPIO Configuration
    PA2     ------> ADC1_IN3
    PB1     ------> ADC1_IN12
    PB12     ------> ADC1_IN11
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2);

    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1|GPIO_PIN_12);

    /* ADC1 interrupt Deinit */
  /* USER CODE BEGIN ADC1:ADC1_2_IRQn disable */
    /**
    * Uncomment the line below to disable the "ADC1_2_IRQn" interrupt
    * Be aware, disabling shared interrupt may affect other IPs
    */
    /* HAL_NVIC_DisableIRQ(ADC1_2_IRQn); */
  /* USER CODE END ADC1:ADC1_2_IRQn disable */

  /* USER CODE BEGIN ADC1_MspDeInit 1 */

  /* USER CODE END ADC1_MspDeInit 1 */
  }
  else if(adcHandle->Instance==ADC2)
  {
  /* USER CODE BEGIN ADC2_MspDeInit 0 */

  /* USER CODE END ADC2_MspDeInit 0 */
    /* Peripheral clock disable */
    HAL_RCC_ADC12_CLK_ENABLED--;
    if(HAL_RCC_ADC12_CLK_ENABLED==0){
      __HAL_RCC_ADC12_CLK_DISABLE();
    }

    /**ADC2 GPIO Configuration
    PA0     ------> ADC2_IN1
    PA6     ------> ADC2_IN3
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_6);

    /* ADC2 interrupt Deinit */
  /* USER CODE BEGIN ADC2:ADC1_2_IRQn disable */
    /**
    * Uncomment the line below to disable the "ADC1_2_IRQn" interrupt
    * Be aware, disabling shared interrupt may affect other IPs
    */
    /* HAL_NVIC_DisableIRQ(ADC1_2_IRQn); */
  /* USER CODE END ADC2:ADC1_2_IRQn disable */

  /* USER CODE BEGIN ADC2_MspDeInit 1 */

  /* USER CODE END ADC2_MspDeInit 1 */
  }
}

/* USER CODE BEGIN 1 */

/* USER CODE END 1 */
FOC_Clark_Park/Core/Src/adc.c10.6 KB
/* USER CODE BEGIN Header */
/**
  ******************************************************************************
  * @file    adc.c
  * @brief   This file provides code for the configuration
  *          of the ADC instances.
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2025 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "adc.h"

/* USER CODE BEGIN 0 */

/* USER CODE END 0 */

ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc2;

/* ADC1 init function */
void MX_ADC1_Init(void)
{

  /* USER CODE BEGIN ADC1_Init 0 */

  /* USER CODE END ADC1_Init 0 */

  ADC_MultiModeTypeDef multimode = {0};
  ADC_InjectionConfTypeDef sConfigInjected = {0};
  ADC_ChannelConfTypeDef sConfig = {0};

  /* USER CODE BEGIN ADC1_Init 1 */

  /* USER CODE END ADC1_Init 1 */

  /** Common config
  */
  hadc1.Instance = ADC1;
  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;
  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
  hadc1.Init.GainCompensation = 0;
  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
  hadc1.Init.LowPowerAutoWait = DISABLE;
  hadc1.Init.ContinuousConvMode = DISABLE;
  hadc1.Init.NbrOfConversion = 1;
  hadc1.Init.DiscontinuousConvMode = DISABLE;
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
  hadc1.Init.DMAContinuousRequests = DISABLE;
  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
  hadc1.Init.OversamplingMode = DISABLE;
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure the ADC multi-mode
  */
  multimode.Mode = ADC_MODE_INDEPENDENT;
  if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Injected Channel
  */
  sConfigInjected.InjectedChannel = ADC_CHANNEL_3;
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_1;
  sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_6CYCLES_5;
  sConfigInjected.InjectedSingleDiff = ADC_SINGLE_ENDED;
  sConfigInjected.InjectedOffsetNumber = ADC_OFFSET_NONE;
  sConfigInjected.InjectedOffset = 0;
  sConfigInjected.InjectedNbrOfConversion = 2;
  sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
  sConfigInjected.AutoInjectedConv = DISABLE;
  sConfigInjected.QueueInjectedContext = DISABLE;
  sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJEC_T1_CC4;
  sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONV_EDGE_RISING;
  sConfigInjected.InjecOversamplingMode = DISABLE;
  if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Injected Channel
  */
  sConfigInjected.InjectedChannel = ADC_CHANNEL_12;
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_2;
  if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_11;
  sConfig.Rank = ADC_REGULAR_RANK_1;
  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
  sConfig.Offset = 0;
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN ADC1_Init 2 */

  /* USER CODE END ADC1_Init 2 */

}
/* ADC2 init function */
void MX_ADC2_Init(void)
{

  /* USER CODE BEGIN ADC2_Init 0 */

  /* USER CODE END ADC2_Init 0 */

  ADC_InjectionConfTypeDef sConfigInjected = {0};
  ADC_ChannelConfTypeDef sConfig = {0};

  /* USER CODE BEGIN ADC2_Init 1 */

  /* USER CODE END ADC2_Init 1 */

  /** Common config
  */
  hadc2.Instance = ADC2;
  hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;
  hadc2.Init.Resolution = ADC_RESOLUTION_12B;
  hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
  hadc2.Init.GainCompensation = 0;
  hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
  hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
  hadc2.Init.LowPowerAutoWait = DISABLE;
  hadc2.Init.ContinuousConvMode = DISABLE;
  hadc2.Init.NbrOfConversion = 1;
  hadc2.Init.DiscontinuousConvMode = DISABLE;
  hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
  hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
  hadc2.Init.DMAContinuousRequests = DISABLE;
  hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
  hadc2.Init.OversamplingMode = DISABLE;
  if (HAL_ADC_Init(&hadc2) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Injected Channel
  */
  sConfigInjected.InjectedChannel = ADC_CHANNEL_3;
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_1;
  sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_6CYCLES_5;
  sConfigInjected.InjectedSingleDiff = ADC_SINGLE_ENDED;
  sConfigInjected.InjectedOffsetNumber = ADC_OFFSET_NONE;
  sConfigInjected.InjectedOffset = 0;
  sConfigInjected.InjectedNbrOfConversion = 1;
  sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
  sConfigInjected.AutoInjectedConv = DISABLE;
  sConfigInjected.QueueInjectedContext = DISABLE;
  sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJEC_T1_CC4;
  sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONV_EDGE_RISING;
  sConfigInjected.InjecOversamplingMode = DISABLE;
  if (HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_1;
  sConfig.Rank = ADC_REGULAR_RANK_1;
  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
  sConfig.Offset = 0;
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN ADC2_Init 2 */

  /* USER CODE END ADC2_Init 2 */

}

static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0;

void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{

  GPIO_InitTypeDef GPIO_InitStruct = {0};
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
  if(adcHandle->Instance==ADC1)
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */

  /** Initializes the peripherals clocks
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
    PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
    {
      Error_Handler();
    }

    /* ADC1 clock enable */
    HAL_RCC_ADC12_CLK_ENABLED++;
    if(HAL_RCC_ADC12_CLK_ENABLED==1){
      __HAL_RCC_ADC12_CLK_ENABLE();
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();
    __HAL_RCC_GPIOB_CLK_ENABLE();
    /**ADC1 GPIO Configuration
    PA2     ------> ADC1_IN3
    PB1     ------> ADC1_IN12
    PB12     ------> ADC1_IN11
    */
    GPIO_InitStruct.Pin = GPIO_PIN_2;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_12;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

    /* ADC1 interrupt Init */
    HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
  /* USER CODE BEGIN ADC1_MspInit 1 */

  /* USER CODE END ADC1_MspInit 1 */
  }
  else if(adcHandle->Instance==ADC2)
  {
  /* USER CODE BEGIN ADC2_MspInit 0 */

  /* USER CODE END ADC2_MspInit 0 */

  /** Initializes the peripherals clocks
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
    PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
    {
      Error_Handler();
    }

    /* ADC2 clock enable */
    HAL_RCC_ADC12_CLK_ENABLED++;
    if(HAL_RCC_ADC12_CLK_ENABLED==1){
      __HAL_RCC_ADC12_CLK_ENABLE();
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();
    /**ADC2 GPIO Configuration
    PA0     ------> ADC2_IN1
    PA6     ------> ADC2_IN3
    */
    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_6;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

    /* ADC2 interrupt Init */
    HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
  /* USER CODE BEGIN ADC2_MspInit 1 */

  /* USER CODE END ADC2_MspInit 1 */
  }
}

void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
{

  if(adcHandle->Instance==ADC1)
  {
  /* USER CODE BEGIN ADC1_MspDeInit 0 */

  /* USER CODE END ADC1_MspDeInit 0 */
    /* Peripheral clock disable */
    HAL_RCC_ADC12_CLK_ENABLED--;
    if(HAL_RCC_ADC12_CLK_ENABLED==0){
      __HAL_RCC_ADC12_CLK_DISABLE();
    }

    /**ADC1 GPIO Configuration
    PA2     ------> ADC1_IN3
    PB1     ------> ADC1_IN12
    PB12     ------> ADC1_IN11
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2);

    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1|GPIO_PIN_12);

    /* ADC1 interrupt Deinit */
  /* USER CODE BEGIN ADC1:ADC1_2_IRQn disable */
    /**
    * Uncomment the line below to disable the "ADC1_2_IRQn" interrupt
    * Be aware, disabling shared interrupt may affect other IPs
    */
    /* HAL_NVIC_DisableIRQ(ADC1_2_IRQn); */
  /* USER CODE END ADC1:ADC1_2_IRQn disable */

  /* USER CODE BEGIN ADC1_MspDeInit 1 */

  /* USER CODE END ADC1_MspDeInit 1 */
  }
  else if(adcHandle->Instance==ADC2)
  {
  /* USER CODE BEGIN ADC2_MspDeInit 0 */

  /* USER CODE END ADC2_MspDeInit 0 */
    /* Peripheral clock disable */
    HAL_RCC_ADC12_CLK_ENABLED--;
    if(HAL_RCC_ADC12_CLK_ENABLED==0){
      __HAL_RCC_ADC12_CLK_DISABLE();
    }

    /**ADC2 GPIO Configuration
    PA0     ------> ADC2_IN1
    PA6     ------> ADC2_IN3
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_6);

    /* ADC2 interrupt Deinit */
  /* USER CODE BEGIN ADC2:ADC1_2_IRQn disable */
    /**
    * Uncomment the line below to disable the "ADC1_2_IRQn" interrupt
    * Be aware, disabling shared interrupt may affect other IPs
    */
    /* HAL_NVIC_DisableIRQ(ADC1_2_IRQn); */
  /* USER CODE END ADC2:ADC1_2_IRQn disable */

  /* USER CODE BEGIN ADC2_MspDeInit 1 */

  /* USER CODE END ADC2_MspDeInit 1 */
  }
}

/* USER CODE BEGIN 1 */

/* USER CODE END 1 */
FOC_Clark/Core/Src/adc.c10.6 KB
/* USER CODE BEGIN Header */
/**
  ******************************************************************************
  * @file    adc.c
  * @brief   This file provides code for the configuration
  *          of the ADC instances.
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2025 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "adc.h"

/* USER CODE BEGIN 0 */

/* USER CODE END 0 */

ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc2;

/* ADC1 init function */
void MX_ADC1_Init(void)
{

  /* USER CODE BEGIN ADC1_Init 0 */

  /* USER CODE END ADC1_Init 0 */

  ADC_MultiModeTypeDef multimode = {0};
  ADC_InjectionConfTypeDef sConfigInjected = {0};
  ADC_ChannelConfTypeDef sConfig = {0};

  /* USER CODE BEGIN ADC1_Init 1 */

  /* USER CODE END ADC1_Init 1 */

  /** Common config
  */
  hadc1.Instance = ADC1;
  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;
  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
  hadc1.Init.GainCompensation = 0;
  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
  hadc1.Init.LowPowerAutoWait = DISABLE;
  hadc1.Init.ContinuousConvMode = DISABLE;
  hadc1.Init.NbrOfConversion = 1;
  hadc1.Init.DiscontinuousConvMode = DISABLE;
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
  hadc1.Init.DMAContinuousRequests = DISABLE;
  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
  hadc1.Init.OversamplingMode = DISABLE;
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure the ADC multi-mode
  */
  multimode.Mode = ADC_MODE_INDEPENDENT;
  if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Injected Channel
  */
  sConfigInjected.InjectedChannel = ADC_CHANNEL_3;
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_1;
  sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_6CYCLES_5;
  sConfigInjected.InjectedSingleDiff = ADC_SINGLE_ENDED;
  sConfigInjected.InjectedOffsetNumber = ADC_OFFSET_NONE;
  sConfigInjected.InjectedOffset = 0;
  sConfigInjected.InjectedNbrOfConversion = 2;
  sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
  sConfigInjected.AutoInjectedConv = DISABLE;
  sConfigInjected.QueueInjectedContext = DISABLE;
  sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJEC_T1_CC4;
  sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONV_EDGE_RISING;
  sConfigInjected.InjecOversamplingMode = DISABLE;
  if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Injected Channel
  */
  sConfigInjected.InjectedChannel = ADC_CHANNEL_12;
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_2;
  if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_11;
  sConfig.Rank = ADC_REGULAR_RANK_1;
  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
  sConfig.Offset = 0;
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN ADC1_Init 2 */

  /* USER CODE END ADC1_Init 2 */

}
/* ADC2 init function */
void MX_ADC2_Init(void)
{

  /* USER CODE BEGIN ADC2_Init 0 */

  /* USER CODE END ADC2_Init 0 */

  ADC_InjectionConfTypeDef sConfigInjected = {0};
  ADC_ChannelConfTypeDef sConfig = {0};

  /* USER CODE BEGIN ADC2_Init 1 */

  /* USER CODE END ADC2_Init 1 */

  /** Common config
  */
  hadc2.Instance = ADC2;
  hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;
  hadc2.Init.Resolution = ADC_RESOLUTION_12B;
  hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
  hadc2.Init.GainCompensation = 0;
  hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
  hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
  hadc2.Init.LowPowerAutoWait = DISABLE;
  hadc2.Init.ContinuousConvMode = DISABLE;
  hadc2.Init.NbrOfConversion = 1;
  hadc2.Init.DiscontinuousConvMode = DISABLE;
  hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
  hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
  hadc2.Init.DMAContinuousRequests = DISABLE;
  hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
  hadc2.Init.OversamplingMode = DISABLE;
  if (HAL_ADC_Init(&hadc2) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Injected Channel
  */
  sConfigInjected.InjectedChannel = ADC_CHANNEL_3;
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_1;
  sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_6CYCLES_5;
  sConfigInjected.InjectedSingleDiff = ADC_SINGLE_ENDED;
  sConfigInjected.InjectedOffsetNumber = ADC_OFFSET_NONE;
  sConfigInjected.InjectedOffset = 0;
  sConfigInjected.InjectedNbrOfConversion = 1;
  sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
  sConfigInjected.AutoInjectedConv = DISABLE;
  sConfigInjected.QueueInjectedContext = DISABLE;
  sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJEC_T1_CC4;
  sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONV_EDGE_RISING;
  sConfigInjected.InjecOversamplingMode = DISABLE;
  if (HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected) != HAL_OK)
  {
    Error_Handler();
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_1;
  sConfig.Rank = ADC_REGULAR_RANK_1;
  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
  sConfig.Offset = 0;
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN ADC2_Init 2 */

  /* USER CODE END ADC2_Init 2 */

}

static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0;

void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{

  GPIO_InitTypeDef GPIO_InitStruct = {0};
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
  if(adcHandle->Instance==ADC1)
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */

  /** Initializes the peripherals clocks
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
    PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
    {
      Error_Handler();
    }

    /* ADC1 clock enable */
    HAL_RCC_ADC12_CLK_ENABLED++;
    if(HAL_RCC_ADC12_CLK_ENABLED==1){
      __HAL_RCC_ADC12_CLK_ENABLE();
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();
    __HAL_RCC_GPIOB_CLK_ENABLE();
    /**ADC1 GPIO Configuration
    PA2     ------> ADC1_IN3
    PB1     ------> ADC1_IN12
    PB12     ------> ADC1_IN11
    */
    GPIO_InitStruct.Pin = GPIO_PIN_2;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_12;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

    /* ADC1 interrupt Init */
    HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
  /* USER CODE BEGIN ADC1_MspInit 1 */

  /* USER CODE END ADC1_MspInit 1 */
  }
  else if(adcHandle->Instance==ADC2)
  {
  /* USER CODE BEGIN ADC2_MspInit 0 */

  /* USER CODE END ADC2_MspInit 0 */

  /** Initializes the peripherals clocks
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
    PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
    {
      Error_Handler();
    }

    /* ADC2 clock enable */
    HAL_RCC_ADC12_CLK_ENABLED++;
    if(HAL_RCC_ADC12_CLK_ENABLED==1){
      __HAL_RCC_ADC12_CLK_ENABLE();
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();
    /**ADC2 GPIO Configuration
    PA0     ------> ADC2_IN1
    PA6     ------> ADC2_IN3
    */
    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_6;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

    /* ADC2 interrupt Init */
    HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
  /* USER CODE BEGIN ADC2_MspInit 1 */

  /* USER CODE END ADC2_MspInit 1 */
  }
}

void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
{

  if(adcHandle->Instance==ADC1)
  {
  /* USER CODE BEGIN ADC1_MspDeInit 0 */

  /* USER CODE END ADC1_MspDeInit 0 */
    /* Peripheral clock disable */
    HAL_RCC_ADC12_CLK_ENABLED--;
    if(HAL_RCC_ADC12_CLK_ENABLED==0){
      __HAL_RCC_ADC12_CLK_DISABLE();
    }

    /**ADC1 GPIO Configuration
    PA2     ------> ADC1_IN3
    PB1     ------> ADC1_IN12
    PB12     ------> ADC1_IN11
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2);

    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1|GPIO_PIN_12);

    /* ADC1 interrupt Deinit */
  /* USER CODE BEGIN ADC1:ADC1_2_IRQn disable */
    /**
    * Uncomment the line below to disable the "ADC1_2_IRQn" interrupt
    * Be aware, disabling shared interrupt may affect other IPs
    */
    /* HAL_NVIC_DisableIRQ(ADC1_2_IRQn); */
  /* USER CODE END ADC1:ADC1_2_IRQn disable */

  /* USER CODE BEGIN ADC1_MspDeInit 1 */

  /* USER CODE END ADC1_MspDeInit 1 */
  }
  else if(adcHandle->Instance==ADC2)
  {
  /* USER CODE BEGIN ADC2_MspDeInit 0 */

  /* USER CODE END ADC2_MspDeInit 0 */
    /* Peripheral clock disable */
    HAL_RCC_ADC12_CLK_ENABLED--;
    if(HAL_RCC_ADC12_CLK_ENABLED==0){
      __HAL_RCC_ADC12_CLK_DISABLE();
    }

    /**ADC2 GPIO Configuration
    PA0     ------> ADC2_IN1
    PA6     ------> ADC2_IN3
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_6);

    /* ADC2 interrupt Deinit */
  /* USER CODE BEGIN ADC2:ADC1_2_IRQn disable */
    /**
    * Uncomment the line below to disable the "ADC1_2_IRQn" interrupt
    * Be aware, disabling shared interrupt may affect other IPs
    */
    /* HAL_NVIC_DisableIRQ(ADC1_2_IRQn); */
  /* USER CODE END ADC2:ADC1_2_IRQn disable */

  /* USER CODE BEGIN ADC2_MspDeInit 1 */

  /* USER CODE END ADC2_MspDeInit 1 */
  }
}

/* USER CODE BEGIN 1 */

/* USER CODE END 1 */

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